Programmable processor cores may be utilized to execute groups or blocks of instructions as atomic units. Such instructions are mapped to the functional units in the cores and significant efficiencies can often be realized when execution loops are created in which the same process is repeated over and over. New data may be continually received and processed as a stream without the need to fetch new instructions. While efficiency is improved in this way, the typical communications paths that are utilized to carry the instructions, for example over a bypass network, are comparatively inefficient.
This Background is provided to introduce a brief context for the Summary and Detailed Description that follow. This Background is not intended to be an aid in determining the scope of the claimed subject matter nor be viewed as limiting the claimed subject matter to implementations that solve any or all of the disadvantages or problems presented above.